ScienceWeek

MATERIALS SCIENCE: ON SCALING DOWN SILICON DEVICES

The following points are made by M. Ieong et al (Science 2004 306:2057):

1) The steady reduction in the minimum feature size in integrated circuits has helped the microelectronic industry to produce products with spectacular increase in computational capability and integration density at lower cost. Smaller transistors operate faster than larger ones, and for a given chip technology, the cost of a chip decreases with area rather than with the number of transistors.

2) The exponential scaling trend surely will eventually hit fundamental limits, but the many predictions of a near-term end of device scaling have proven too pessimistic. With the introduction of the production of 90-nm node technology in 2004, the semiconductor industry is entering the "nano" era [1]. (The "90-nm node" refers to the smallest half-pitch metal lines available in the technology. The actual gate lengths of the devices are about 50 nm.) In the next decade, device gate lengths will be scaled to below 10 nm [1].

3) The MOSFET, or metal oxide semiconductor field-effect transistor, is a fundamental switching device in very-large-scale integrated (VLSI) circuits. A MOSFET has at least three terminals, which are designated as gate, source, and drain. The gate electrode is separated electrically from the source and the drain by a thin dielectric film, usually silicon dioxide. The source and the drain are doped with impurities that are opposite in polarity to the substrate, which is doped with boron for N-channel transistors and with arsenic or phosphorous for P-channel transistors. This source, substrate, and drain doping effectively produces two back-to-back junction diodes from the source terminal to the drain terminal. When a sufficiently large positive voltage is applied to the gate of an N-channel transistor (which creates an electric field, hence the field effect), the silicon surface is "inverted" -- the conduction band is populated and forms a narrow conducting layer between the source and the drain. If there is a voltage difference between the source and the drain, an electric current can flow between them. When the gate voltage is removed or set at zero voltage, the surface region under the gate is depleted with electric carriers and there is no current flow between the source and the drain. The current flowing through the structure can thus be regulated by applying voltage to the gate electrode.

4) A MOSFET can be used either as an electrical switch or as an amplifier. The majority of MOSFETs on an integrated circuit today are used as electrical switches. How fast a MOSFET can be switched on and off is therefore a critical figure of merit to determine the competitiveness of the technology. The two major factors that control the speed of MOSFETs are the channel length from the source to the drain and the speed at which channel charge carriers travel from the source to the drain.

5) In summary: In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations.[2-5]

References (abridged):

1. Semiconductor Industry Association, International Technology Roadmap for Semiconductors (2003); available at http://public.itrs.net.

2. R. H. Dennard et al., IEEE J. Solid-State Circuits 9, 256 (1974)

3. Y. Taur, IEEE Spectrum 36, 25 (1999)

4. M.Ieong, J.Kedzierski, Z.Ren, B. Doris, T. Kanarsky, H.-S. P. Wong, Extended Abstract of the 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, 17 to 19 September 2002, pp. 136-137.

5. B. Doris et al., International Electron Device Meeting (IEDM) Tech. Dig. 2002, 267 (2002)

Science http://www.sciencemag.org

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LIMITS OF SILICON NANOELECTRONICS

The following points are made by J.D. Meindl et al (Science 2001 293:2044):

1) Silicon technology has advanced at exponential rates in both performance and productivity throughout the past four decades. From 1960 to 2000, the energy transfer associated with a binary switching transition -- the canonical digital computing operation -- decreased by approximately 5 orders of magnitude and the number of transistors per chip increased by approximately 9 orders of magnitude. But such exponential advances must eventually come to a halt imposed by a hierarchy of physical limits. The 5 levels of this hierarchy are defined as: fundamental, material, device, circuit, and system.

2) A coherent analysis of the key limits of each of these levels reveals that silicon technology has the enormous remaining potential to achieve terascale integration of more than 1 trillion transistors per chip, with critical device dimensions or channel lengths in the 10 nanometer range. This potential represents more than a 3-decade increase in the number of transistors per chip and more than a 1-decade reduction in minimum transistor feature size compared with the state of the art in 2001.

3) Fundamental physical limits that are independent of the characteristics of any particular material, device structure, circuit configuration, or system architecture will be virtually impenetrable barriers to additional advances of terascale integration. But limited terascale integration on a massive scale is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of approximately 1 nanometer, silicon channel thickness of approximately 3 nanometers, and channel length of approximately 10 nanometers. The development of interconnecting wires for these transistors presents a major current challenge to the achievement of nanoelectronics involving terascale integration.

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ON SILICON-BASED QUANTUM COMPUTER ARCHITECTURE

Notes by ScienceWeek:

The indivisible unit of classical information is the "bit", which takes one of two possible values, 0 or 1. Any amount of classical information can be expressed as a sequence of bits.

A classical computer executes a series of simple operations ("gates"), each of which acts upon a single bit or pair of bits. By executing many gates in succession, the computer can evaluate any Boolean function of a set of input bits.

Quantum information can also be reduced to elementary units, called quantum bits or "qubits". A qubit is a two-level quantum system (e.g., the spin of an electron). A quantum computer executes a series of elementary quantum gates, each of which is a unitary transformation that acts on a single qubit or pair of qubits. By executing many such gates in succession, the quantum computer can apply a complicated unitary transformation to a particular initial state of a set of qubits. Finally, the qubits can be measured, the measurement outcome the final result of a quantum computation.

In this context, the term "unitary transformation" refers to a linear operator whose adjoint is equal to its inverse. The "adjoint" A* of an operator A is an operator such that for all f and g in the domain of A: (Af,g) = (f,A*g). If A* = A, then A is said to be self-adjoint.

The following points are made by B. Koiller et al (Phys. Rev. Lett. 2002 88:027903):

1) Following the proposal by Kane (1), there has been much effort [2-4] to develop a silicon-based quantum computer architecture. The basic ideas of the Kane proposal are simple and attractive: to use donor nuclear spins as quantum bits (qubits), and to utilize the vast infrastructure and technology associated with the Si industry to fabricate precisely controlled Si nanostructures, where exchange effects between electrons and nuclei in neighboring donor impurities (e.g., P-31 in Si) could serve as the two-qubit gates, similar to the electron-spin-based QC proposal by Loss and DiVincenzo [5]. The motivation for a Si quantum computer is obvious: Once the basic one-qubit and two-qubit operations have been demonstrated using donor impurities in Si nanostructures, computer chip fabrication technology associated with the existing and dominant Si industry will easily enable the scale-up of information processing involving a large number of donor nuclear spin qubits. Indeed, one of the formidable stumbling blocks in developing working quantum computer hardware has been the scale-up problem, as the demonstrated qubits in trapped ion and liquid state NMR techniques are not readily scalable in any significant manner.

2) A great deal of experimental work is currently aimed at developing suitable qubits in Si nanostructures with precisely introduced dopant impurities, using both a "top-down" approach with ion implantation, and a "bottom-up" approach with molecular beam epitaxy growth and scanning tunneling microscopy [4]. In the Si quantum computer model [1,2], donor electrons act as shuttles between different nuclear spins. For two-qubit operations, which are required for a universal quantum computer, both electron-electron exchange and electron-nucleus hyperfine interaction need to be precisely controlled. These are unquestionably formidable experimental problems. In the original proposal, Kane used the Herring-Flicker exchange formula for two hydrogenic centers to obtain an order of magnitude estimate of the electron exchange among donors in Si [1]. However, as he also pointed out, donor exchange in Si is not hydrogenic.

3) The authors report a calculation of the donor electron exchange in silicon and germanium, and demonstrate an atomic-scale challenge for quantum computing in Si (and Ge), as the six (four) conduction-band minima in Si (Ge) lead to intervalley electronic interference, generating strong oscillations in the exchange splitting of two-donor two-electron states. Donor positioning with atomic-scale precision within the unit cell thus becomes a decisive factor in determining the strength of the exchange coupling a fundamental ingredient for two-qubit operations in a silicon-based quantum computer.

References (abridged):

1. B.E. Kane, Nature (London) 393, 133 (1998)

2. B. E. Kane, Fortschr. Phys. 48, 1023 (2000)

3. R. Vrijen et al., Phys. Rev. A 62, 012306 (2000)

4. J.L. O'Brien et al.. Phys. Rev. B 64, 161401 (2001)

5. D. Loss and D. P. DiVincenzo, Phys. Rev. A 57, 120 (1998)

Phys. Rev. Lett. http://prl.aps.org

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